1. Field of the Invention
This invention generally relates to digital communications and, more particularly, to a system and method for determining and acquiring the clock frequency of a serial data stream.
2. Description of the Related Art
Digital high-speed communications, either electrical or optical, such as those compliant with the Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) standards, are enabled using a serial data stream. To recover the serial data stream at a receiver, the clock frequency of the received data must first be detected. Typically, the approximate frequency of the serial data stream is known. One common method of providing a data clock is to use a phase-locked loop (PLL) with a voltage controlled oscillator (VCO) to acquire the frequency, and then the phase of the received data.
Voltage controlled ring oscillators are commonly used in monolithic clock data recovery (CDR) units, as they are easy to fabricate and provide reliable results. Voltage controlled ring oscillators can, and usually do exhibit a tuning range much wider than the closed loop PLL bandwidth of the circuits in which they operate.
Clock recovery phase-locked loops (PLLs) generally don't use phase-frequency detectors (PFDs) in the data path since the incoming data signal isn't deterministic. PFDs are more typically used in frequency synthesizers with periodic (deterministic) signals. Clock recovery PLLs use exclusive-OR (XOR)-based phase detectors to maintain quadrature phase alignment between the incoming data pattern and the re-timed pattern. XOR-based phase detectors have a limited frequency discrimination capability, generally restricting frequency offsets to less than the closed loop PLL bandwidth. This characteristic, coupled with the wide tuning range of the VCO, requires CDR circuits to depend upon an auxiliary frequency acquisition system.
There are two basic PLL frequency acquisition techniques. The first is a VCO sweep method. During an out-of-lock condition, auxiliary circuits cause the VCO frequency to slowly sweep across its tuning range in search of an input signal. The sweeping action is halted when a zero-beat note is detected, causing the PLL to lock to the input signal. The VCO sweep method is generally used in microwave frequency synthesis applications. The second type of acquisition aid, commonly found in clock recovery circuits, uses a PFD in combination with an XOR phase detector. When the PLL isn't locked to a data stream, the PLL switches over to a PFD that is driven by a stable reference clock source. The reference clock frequency is approximately equal to the data stream rate. Thus, the VCO frequency is held very close to the data rate. Keeping the VCO frequency in the proper range of operation facilitates acquisition of the serial data and maintains a stable downstream clock when serial data isn't present at the CDR input. When serial data is applied to the CDR, the XOR based phase detector replaces the PFD, and data re-timing resumes.
However, serial data streams may be clocked at a number of frequencies, depending upon the communication protocol. Due to the PLL constraints mentioned above, a typical receiver is designed to operate at one particular data clock rate. Thus, a conventional receiver necessarily has a limited use. Even if the frequency of use can be selected from a range of potential frequencies, the actual operating frequency that is selected must be pre-programmed.
It would be advantageous if a synchronous serial data stream receiver could be made to operate at a number of different clock rates, without the preliminary step of pre-programming the operating frequency.
It would be advantageous if a synchronous serial data stream receiver could automatically determine the frequency of a received data stream and supply an appropriate data clock to recover the signal.